1. Field of the Invention
The present invention relates to a vertical transistor and a dynamic random access memory (DRAM) structure including therein the vertical transistor.
2. Description of the Prior Art
Along with the miniaturization of various electronic products, the dynamic random access memory (DRAM) elements have to meet the demand of high integration and high density. A DRAM structure includes a capacitor for holding a charge and a transistor for accessing the charge held in the capacitor. DRAMs with trench capacitors or stacked capacitors are widely used in the industry so as to well utilize space of chips to effectively reduce memory cell size. Typically, trench capacitors are fabricated inside deep trenches that are formed in a semiconductor substrate by an etching process, followed by the manufacturing process of transistors. Stacked capacitors are generally formed after formation of transistors, and located on the transistors. There are various stack types, such as, plane, pillar, fin-type, and cylinder. Also, there are various types of transistors, which may be categorized into two broad categories: planar transistor structures and vertical transistor structures, based upon the orientation of the channel region relative to the primary surface of semiconductor substrate. Specifically, planar transistor devices are devices in which the electric current flows in the gate channel in a direction parallel to the primary surface of the semiconductor substrate, and vertical transistor devices are devices in which the electric current flows in the gate channel in a direction substantially orthogonal to the primary surface of the semiconductor substrate.
Vertical transistors with surrounding gate transistors (SGT) have been applied to a layout with a cell unit of 4 F2. F stands for feature size. Most of these SGT structures have a gate channel formed in the pillar per se, a gate dielectric layer enveloping the pillar on the outer wall, and a gate material layer enveloping the gate dielectric layer to serve as a gate. Accordingly, the gate surrounds the perimeter of the pillar, and the source/drain regions are formed in the top portion and the bottom portion of the pillar, respectively. The pillar can be made by either directly etching a substrate or forming an epitaxial layer followed by etching. The former process can be used for mass production, and the latter process is relatively easier. For example, a memory structure having an SGT structure is disclosed in U.S. Pat. No. 7,042,047, in which a gate surrounds a perimeter of the epitaxial post, i.e. the epitaxial post serves as a gate channel. However, the epitaxial silicon is often inferior in properties to the bulk silicon, such that transistors such obtained tend to be inferior in performance. The SGT also faces a challenge of floating body effect due to the source/drain placed at the top/bottom of the channel. It will induce an uncontrollable device threshold voltage.
Therefore, there is still a need for a novel SGT structure with excellent gate channel properties so as to avoid the floating body effect and a DRAM structure including the same.